SUBJECT NAME: VLSI DESIGN. SUBJECT CODE: EC UNIT I CMOS TECHNOLOGY. PART –A (2 MARKS). 1. What are four generations of Integration. EC / EC64 VLSI Design 2 Marks With Answers ECE 6th Semester Regulation | BE Electronics and Communication Engineering. Sixth Semester. 2 MARK QUESTION AND ANSWERS. ECVLSI DESIGN is CMOS technology? Complementary Metal Oxide Semiconductor (CMOS)in which.
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Verilog supports basic logic gates as predefined primitives. It consists of n input lines and m output lines.
These are especially important tools for layout built from large cells. A device connected so as to pull the output voltage to the lower supply voltage usually 0 V is called pull down device.
Steps to prevent metastability: What is the structural gate-level modeling? What is meant by programmable logic plane? Each node or line to be faulted is set to 0 and then 1 and the test vector set is applied. The test architecture consists of: What are two types of anwers dissipation? What are different generations of integration circuits? Give the classifications of timing control?
EC VLSI DESIGN Important Part A 2 Mark Part B 16 Mark Question Bank
What are the different operating regions foe an MOS transistor? Careful control during fabrication is necessary to avoid this problem. Verilog is a general purpose hardware descriptor language. Performance increase comes at the cost of area. Violate monotonicity during evaluation phase. What is known as percentage-fault coverage? This makes MOS dynamic circuits faster.
First, the node to be faulted is selected. With short channel devices the ratio between the lateral and vertical dimensions are reduced. Multiplexing element of path selector A latch element an unlock switch Act as a voltage controlled resistor connecting the input and output. The boundary scan register is a special case of a data register.
EC – VLSI Design 2Marks with Answer and 16Marks Question
What are the self-test techniques? The effective length of the conductive channel is actually modulated by the applied voltage VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel. What is the TAP controller? What are the applications of chip level test techniques? The observability of a particular internal circuit node is the degree to which one can observe that node at the outputs of an integrated circuit. What is non critical race?
Why is carry bypass Adder called so? Ingot trimming and grinding 3.
If the gate field must induce a channel before current can flow and the gate voltage enhances the channel current and such a device is said to the enhancement mode MOS. The performance and the area of a programmable shifter are dominated by the wiring. If ec235 is false zero or ambiguous xvlwi false- statement is executed. What is the standard cell based ASIC design? By using two operating modes, active and standby for each function blocks. What is a multiplier circuit?
The load capacitance can be reduced to reduce delay this is achieved by using transistor of smaller and smaller dimension by feature generation technology.
What is dynamic power dissipation? Give the different types of ASIC. Logic synthesisSystem partitioning c.